1. Field Of The Invention
The present invention relates to a logic design automation system which uses a computer, and more particularly to updating of gate-level logic in the physical design phase.
2. Description Of The Prior Art
As a digital system has recently been implemented in VLSI's, an automatic logic synthesis system has been developed to improve design quality of the digital system and reduce design manpower required, in which gate-level logic which indicates connection of gates is automatically generated by inputting functional-level logic such as Boolean expression, truth table or standard macro logic into a computer. Since the automatic logic synthesis system handles only logic design information which the system generates by itself such as gate information or interconnecting line information, it is useful in an initial transformation from the functional-level logic to the gate-level logic in the logic design phase prior to physical design. Physical design information such as gate position information, gate replacement information and pin exchange information, and manually optimized logic design information are added in the physical design phase. If the functional-level logic is modified in the physical design phase and the gate-level logic is synthesized by the automatic logic synthesis system from the modified functional-level logic, the information for the portions which need not be modified are lost.
In order to resolve the above problem, it is necessary to automatically identify the portions of the current gate-level logic which need not be modified and bring them in the updated gate-level logic. However, such a method has not been available. Methods for automatically verifying logical equivalency between logic functions are disclosed in the following articles but they are not sufficient to resolve the problem. Article 1: "Boolean Comparison of Hardware and Flowcharts" by G. L. Smith et al, IBM J. Res. Develop., Vol. 26, No. 1, January 1982, pages 106 - 116. Article 2: "A Procedure for Functional Design Verification" by S. B. Akers, 10th FTCS, 1980, pages 65 - 67.